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Preliminary Technical Data
FEATURES
Quad, 12-/14-/16-Bit nanoDACs(R) with 5ppm/C On-chip Ref, I2C Interface AD5625R/AD5645R/AD5665R AD5625/AD5665
VDD GND V REFIN /VREFOUT 1.25V/2.5V REF DAC REGISTER STRING DAC A
Low power, smallest pin-compatible, quad nanoDACs AD5625R/AD5645R/AD5665R 12-/14-/16 bits On-chip 1.25 V/2.5 V, 5 ppm/C reference. AD5625/AD5665 12-/16 bits External reference only 3 mm x 3 mm LFCSP and 14-lead TSSOP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale/midscale Per channel power-down I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes
AD5625R/AD5645R/AD5665R
INPUT REGISTER ADDR1 ADDR2 SCL INTERFACE LOGIC INPUT REGISTER SDA INPUT REGISTER POWER-ON RESET LDAC CLR POR DAC REGISTER STRING DAC D DAC REGISTER STRING DAC C INPUT REGISTER DAC REGISTER STRING DAC B
BUFFER
V OUTA
BUFFER
V OUTB
BUFFER
V OUTC
BUFFER
VO UTD
POWER-DOWN LOGIC
NOTE. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-PIN PACKAGE - ADDR2, LDAC, CLR, POR. V REFIN VDD GND
AD5625/AD5665
INPUT REGISTER ADDR1 DAC REGISTER STRING DAC A BUFFER V OUTA
APPLICATIONS
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
ADDR2 SCL INTERFACE LOGIC
INPUT REGISTER
DAC REGISTER
STRING DAC B
BUFFER
V OUTB
INPUT REGISTER SDA INPUT REGISTER POWER-ON RESET LDAC CLR POR
DAC REGISTER
STRING DAC C
BUFFER
V OUTC
DAC REGISTER
STRING DAC D
BUFFER
VO UTD
POWER-DOWN LOGIC
NOTE. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-PIN PACKAGE - ADDR2, LDAC, CLR, POR.
Figure 1. Functional Block Diagrams
GENERAL DESCRIPTION
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 members of the nanoDAC family, are low power, quad, 12-, 14-, 16-bit buffered voltage-out DACs with/without an on-chip reference. All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design and have an I2Ccompatible serial interface . The AD5625R/AD5645R/AD5665R have an on-chip reference. The AD56x5RBCPZ have a 1.25 V, 5 ppm/C reference, giving a full-scale output range of 2.5 V; the AD56x5RBRUZ have a 2.5 V, 5 ppm/C reference giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5665 and AD5625 require an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V or midscale and remains there
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The on-chip precision output amplifier enables rail-to-rail output swing. The AD5625R/AD5645R/AD5665R, AD5625/AD5665 use a 2wire I2C-compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. Table 1. Related Devices
Part No. AD5624R/AD5644R/AD5664R AD5624/AD5664 AD5627R/AD5647R/AD5667R AD5627/5667, AD5666 Description Quad SPI 12-, 14-, 16-bit DACs, with/without internal reference. Dual I2C 12-, 14-,16-bit DACs, with/without internal reference. 2.7 V to 5.5 V, Quad 16-bit DAC, internal reference, SPI interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
TABLE OF CONTENTS Features...................................................................................1 Applications ...........................................................................1 General Description .............................................................1 Product Highlights................................................................1 Table1. Related Devices ........................................................2 TABLE OF CONTENTS ......................................................2 Specifications .........................................................................3 AC Characteristics ................................................................4 I C Timing Specifications.....................................................5 Absolute Maximum Ratings ................................................7 Pin Configuration and Function Descriptions..................8 Typical Performance Characteristics ..................................9 Terminology...........................................................................17 Theory of Operation .............................................................19 D/A Section............................................................................19 Resistor String........................................................................19 Output Amplifier...................................................................19 Internal Reference .................................................................19 External Reference ................................................................19 Serial Interface .......................................................................19 REVISION HISTORY
4/06--Revision 0: Initial Version
2
Preliminary Technical Data
Write Operation.....................................................................21 Read Operation......................................................................21 High Speed Mode ..................................................................22 Multiple Byte Write ...............................................................23 Broadcast Mode .....................................................................23 Input Shift Register................................................................23 Write Commands and LDAC...............................................24 LDAC Setup............................................................................24
LDAC Pin.................................................................................25
Power-Down Modes..............................................................25 Power-on Reset and Software Reset ....................................26 Internal Reference Setup.......................................................26 Clear Pin (CLR) .....................................................................26 Applications............................................................................27 Using A Reference as Power Supply ....................................27 Bipolar Operation..................................................................27 Power Supply Bypassing and Grounding ...........................27 Outline Dimensions ..............................................................28 Ordering Information ...........................................................29
Rev. PrA. | Page 2 of 32
Preliminary Technical Data
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Specifications: AD5625R/AD5645R/AD5665R, AD5625/AD5665
VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE2 AD5665R/AD5665 Resolution Relative Accuracy Differential Nonlinearity AD5645R Resolution Relative Accuracy Differential Nonlinearity AD5625R/AD5625 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature DC Power Supply Rejection DC Crosstalk (External Reference) Min B Grade1 Typ Max Unit Conditions/Comments
16 8 16 1
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV mV % of FSR % of FSR V/C ppm dB V V/mA V V V/mA V
Guaranteed monotonic by design
14 2 4 0.5
Guaranteed monotonic by design
12 0.5 2 1 -0.1 2 2.5 -100 10 10 5 25 20 10 1 0.25 10 10 1 1.5
Guaranteed monotonic by design All zeroes loaded to DAC register All ones loaded to DAC register
Of FSR/C DAC code = midscale ; VDD = 5V 10% Due to full-scale output change, Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel)
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT (LFCSP PACKAGE) Output Voltage Reference TC3 Output Impedance REFERENCE OUTPUT (TSSOP PACKAGE) Output Voltage Reference TC3 Output Impedance
0 2 10 0.5 30 4 170 0.75 26
VDD
V nF nF mA s A V k
RL = RL = 2 k VDD = 5 V Coming out of power-down mode; VDD = +5 V VREF = VDD = 5.5 V
200 VDD
1.247 10 7.5
1.253
V ppm/C k
At ambient
2.495 5 7.5
2.505 10
V ppm/C k
At ambient
Rev. PrA. | Page 3 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Parameter Min B Grade1 Typ Max Unit
Preliminary Technical Data
Conditions/Comments
LOGIC INPUTS (SDA, SCL) IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC OUTPUTS (OPEN DRAIN) VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output POWER REQUIREMENTS VDD IDD (Normal Mode)4 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes)5
1 2
1 0.3 x VDD 0.7 x VDD 2 0.1 x VDD 0.4 0.6 1 2
A V V pF V V V A pF ISINK = 3 mA ISINK = 6 mA
2.7 0.45 0.44 0.95 0.95 0.48
5.5 0.55 0.5 1.2 1.15 1
V mA mA mA mA A VIH = VDD, VIL = GND Internal reference off Internal reference off Internal reference on Internal reference on VIH = VDD, VIL = GND
Temperature range: B grade: -40C to +105C. Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024); AD5645 (Code 128 to Code 16,256); AD5625 (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.1 Table 4.
Parameter2 Output Voltage Settling Time AD5625R/AD5625 AD5645R AD5665R/AD5665 Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise
1 2
Min
Typ 3 3.5 4 1.8 10 0.1 -90 0.1 1 4 1 4 340 -80 120 100 15
Max 4.5 5 7
Unit s s s V/s nV-s nV-s dBs nV-s nV-s nV-s nV-s nV-s kHz dB nV/Hz nV/Hz V p-p
Conditions/Comments3 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 2 LSB 1 LSB change around major carry VREF = 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference VREF = 2 V 0.1 V p-p VREF = 2 V 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz
Guaranteed by design and characterization, not production tested. See the Terminology section.
Rev. PrA. | Page 4 of 32
Preliminary Technical Data
3
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Temperature range is -40C to +105C, typical at 25C.
Rev. PrA. | Page 5 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1 Table 5.
Parameter fSCL3 Conditions2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Limit at TMIN, TMAX Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 3.45 0 0.9 0 70 0 150 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 1000 300 80 160 300 300 80 160 1000 300 40 80 1000 300 80 160 Unit KHz KHz MHz MHz s s
Preliminary Technical Data
Description Serial clock frequency
t1
tHIGH, SCL high time ns ns tLOW, SCL low time
t2
t3
t4
t5
t6
t7
s s ns ns ns ns ns s s ns ns s s ns s s ns s s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, set-up time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start condition tSU;STO, setup time for a stop condition
t8
t9
tRDA, rise time of SDA signal
10 20
t10
tFDA, fall time of SDA signal
10 20
t11
tRCL, rise time of SCL signal
10 20
t11A
tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
10 20
Rev. PrA. | Page 6 of 32
Preliminary Technical Data
Parameter t12 Conditions2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Fast mode High speed mode
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Limit at TMIN, TMAX Min Max 300 300 10 40 20 80 0 50 0 10 Unit ns ns ns ns ns ns Description tFCL, fall time of SCL signal
tSP4
1 2
Pulse width of spike suppressed
See Figure 2. High speed mode timing specification applies only to the AD5625BRUZ-2 and AD5665BRUZ-2. CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. PrA. | Page 7 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP_WD Package (4-Layer Board) JA Thermal Impedance TSSOP Package JA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -65C to +150C 150C (TJ max - TA)/JA 61C/W 150.4C/W 260C 5C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA. | Page 8 of 32
Preliminary Technical Data
AD5625R/AD5645R/AD5665R, AD5625/AD5665
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC 1 ADDR1 2 V DD 3 V OUT A 4 V OUT C 5 VREFIN/ VREFOUT 7 14 SCL
V OUT A 1 V OUT B 2 GND 3 V OUT C 4 V OUT D 5
AD5625(R) AD5645R AD5665(R)
13 SDA 12 GND 11 V OUT B
AD5625(R) AD5645R AD5665(R)
TOP VIEW (Not to Scale)
10 V REFIN/ V REFOUT 9 V DD 8 SDA 7 SCL 6 ADDR
TOP VIEW 10 V OUT D (Not to Scale) 9 CLR POR 6 8 ADDR2
NOTE: V REFOUT ONLY ON -R VERSIONS
NOTE: V REFOUT ONLY ON -R VERSIONS
Pin Configuration (14-pin) Figure 3. Pin Configurations
Pin Configuration (10-pin)
Table 7. Pin Function Descriptions
Pin No. (14-pin) 1 2 3 4 5 6 7 Pin No. (10-pin) n/a n/a 9 1 4 n/a 10 Mnemonic Description
LDAC
ADDR1 VDD VOUTA VOUTC POR VREFIN/VREFOUT
Active low load DAC pin. Three-state address input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6). Power supply input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Analog output voltage from DAC C. The output amplifier has rail-to-rail operation. Analog output voltage from DAC D. The output amplifier has rail-to-rail operation. Power-on reset. The AD5625R/AD5645R/AD5665R, AD5625/AD5665 have a common pin for reference input and reference output. The internal reference and reference output are only available on suffix -- R versions. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Three-state address input. Sets bits A3 and A2 of the 7-bit slave address (see Table 6). Asynchronous clear input. The CLR input is falling edge sensitive. . While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. Analog output voltage from DAC A. The output amplifier has rail-to-rail operation. Analog output voltage from DAC B. The output amplifier has rail-to-rail operation. Ground reference point for all circuitry on the part. Serial data line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial clock line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. Three-state address input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
8 9
n/a n/a
ADDR2
CLR
10 11 12 13
5 2 3 8
VOUTD VOUTB GND SDA
14 n/a
7 6
SCL ADDR
Rev. PrA. | Page 9 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665 TYPICAL PERFORMANCE CHARACTERISTICS
10 8 6
DNL ERROR (LSB) INL ERROR (LSB)
Preliminary Technical Data
1.0
VDD = VREF = 5V TA = 25C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
05858-005
VDD = VREF = 5V TA = 25C
4 2 0 -2 -4 -6 -8 -10 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE
-1.0
0
10k
20k
30k CODE
40k
50k
60k
Figure 4. INL AD5665, External Reference
4 3 2 1 0 -1 -2
-0.3
05856-005
Figure 7. DNL AD5665, External Reference
0.5 0.4 0.3
DNL ERROR (LSB)
VDD = VREF = 5V TA = 25C
VDD = VREF = 5V TA = 25C
0.2 0.1 0 -0.1 -0.2
INL ERROR (LSB)
-0.4 -0.5 0 2500 5000 7500 10000 CODE 12500 15000
-4
0
2500
5000
7500 10000 CODE
12500
15000
Figure 5. INL AD5645, External Reference
1.0 VDD = VREF = 5V 0.8 TA = 25C 0.6
DNL ERROR (LSB)
Figure 8. DNL AD5645, External Reference
0.20 0.15 0.10 0.05 0 -0.05 -0.10
05856-009
VDD = VREF = 5V TA = 25C
0.4
INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-006
-0.15 -0.20
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
Figure 6. INL AD5625, External Reference
Figure 9. DNL AD5625, External Reference
Rev. PrA. | Page 10 of 32
05856-008
-3
05856-007
Preliminary Technical Data
10 8 6
INL ERROR (LSB)
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1.0 0.8 0.6
DNL ERROR (LSB)
VDD = 5V VREFOUT = 2.5V TA = 25C
VDD = 5V VREFOUT = 2.5V TA = 25C
4 2 0 -2 -4 -6 -8 -10
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-010
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-013
CODE
CODE
Figure 10. INL AD5665R, 2.5V Internal Reference
4 3 2 1 0 -1 -2
-0.3 -0.4 -0.5 0.5
Figure 13. DNL AD5665R, 2.5V Internal Reference
VDD = 5V VREFOUT = 2.5V TA = 25C
VDD = 5V VREFOUT = 2.5V TA = 25C
0.4 0.3
DNL ERROR (LSB)
INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2
0
0
-4
1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 15000 16250
05856-011
1250
2500
3750
5000
6250
7500
8750
10000
11250
12500
13750
15000
CODE
CODE
Figure 11. INL AD5645R, 2.5V Internal Reference
1.0 0.8 0.6
INL ERROR (LSB)
Figure 14. DNL AD5645R, 2.5V Internal Reference
0.20 VDD = 5V VREFOUT = 2.5V TA = 25C
VDD = 5V VREFOUT = 2.5V TA = 25C
0.15 0.10
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-012
0.05 0 -0.05 -0.10
05856-015
-0.15 -0.20
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
Figure 12. INL AD5625R, 2.V5 Internal Reference
Figure 15. DNL AD5625R, 2.5V Internal Reference
Rev. PrA. | Page 11 of 32
16250
05856-014
-3
AD5625R/AD5645R/AD5665R, AD5625/AD5665
10 8 6
INL ERROR (LSB)
Preliminary Technical Data
1.0 0.8 0.6
DNL ERROR (LSB)
VDD = 3V VREFOUT = 1.25V TA = 25C
VDD = 3V VREFOUT = 1.25V TA = 25C
4 2 0 -2 -4 -6 -8 -10
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-016
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000 16250
05856-019 05856-021 05856-020
CODE
CODE
Figure 16. INL AD5665R,1.25V Internal Reference
4 3 2 1 0 -1 -2 -0.3
05856-017
Figure 19. DNL AD5665R,1.25V Internal Reference
0.5 VDD = 3V VREFOUT = 1.25V TA = 25C
VDD = 3V VREFOUT = 1.25V TA = 25C
0.4 0.3
DNL ERROR (LSB)
INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2
-3 -4
0 11250 1250 2500 3750 5000 6250 7500 8750 10000 12500 13750 15000 16250
-0.4 -0.5
0 10000 11250 1250 2500 3750 5000 6250 7500 8750 12500 13750 15000
CODE
CODE
Figure 17. INL AD5645R, 1.25V Internal Reference
1.0 0.8 0.6
INL ERROR (LSB)
Figure 20. DNL AD5645R,1.25V Internal Reference
0.20 VDD = 3V VREFOUT = 1.25V TA = 25C
VDD = 3V VREFOUT = 1.25V TA = 25C
0.15 0.10
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-018
0.05 0 -0.05 -0.10 -0.15 -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
-1.0
Figure 18. INL AD5625R,1.25V Internal Reference
Figure 21. DNL AD5625R, 1.25V Internal Reference
Rev. PrA. | Page 12 of 32
Preliminary Technical Data
8 6 VDD = VREF = 5V 4 MAX INL
AD5625R/AD5645R/AD5665R, AD5625/AD5665
0 -0.02 -0.04 -0.06 VDD = 5V
GAIN ERROR
ERROR (LSB)
2 MAX DNL 0 -2 -4 MIN INL
05856-022
ERROR (% FSR)
-0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -20 0 20 40 60 TEMPERATURE (C) 80 100
05856-025 05856-027 05856-026
MIN DNL
FULL-SCALE ERROR
-6 -8 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
-0.20 -40
Figure 22. INL Error and DNL Error vs. Temperature
10 8 6 4
ERROR (LSB)
Figure 25. Gain Error and Full-Scale Error vs. Temperature
1.5
MAX INL
1.0 0.5
ZERO-SCALE ERROR
VDD = 5V TA = 25C MAX DNL
ERROR (mV)
2 0 -2 -4 MIN DNL
0 -0.5 -1.0 -1.5
-6 -8 -10 0.75 1.25 1.75 2.25 2.75 3.25 VREF (V) 3.75 MIN INL
-2.0
05856-023
OFFSET ERROR
4.25
4.75
-2.5 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 23. INL and DNL Error vs. VREF Figure 26. Zero-Scale Error and Offset Error vs. Temperature
8 1.0 6 TA = 25C 4 MAX INL 0.5 GAIN ERROR MAX DNL 0 -2 -4 MIN INL -6
05856-024
ERROR (LSB)
ERROR (% FSR)
2
0 FULL-SCALE ERROR -0.5
MIN DNL
-1.0
-1.5 3.2 3.7 4.2 VDD (V) 4.7 5.2
-8 2.7
-2.0 2.7
3.2
3.7
Figure 24. INL and DNL Error vs. Supply
4.2 VDD (V)
4.7
5.2
Figure 27. Gain Error and Full-Scale Error vs. Supply
Rev. PrA. | Page 13 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1.0 TA = 25C 0.5 0 ZERO-SCALE ERROR
8 7 6
Preliminary Technical Data
VDD = 3.6V TA = 25C
FREQUENCY
ERROR (mV)
5 4 3 2
-0.5 -1.0 -1.5 -2.0 -2.5 2.7
OFFSET ERROR
05856-028
0
3.2
3.7
4.2 VDD (V)
4.7
5.2
0.39
0.40
0.41 IDD (mA)
0.42
0.43
Figure 28. Zero-Scale Error and Offset Error vs. Supply
6 5 VDD = 5.5V TA = 25C
Figure 31. IDD Histogram with External Reference, 3.6 V
8 7 6 VDD = 3.6V TA = 25C
FREQUENCY
FREQUENCY
4
5 4 3 2
3 2
05856-029
0
0.41
0.42
0.43 IDD (mA)
0.44
0.45
0
0.90
0.92
0.94 IDD (mA)
0.96
Figure 29. IDD Histogram with External Reference, 5.5 V
6 VDD = 5.5V TA = 25C
Figure 32. IDD Histogram with Internal Reference, VREFOUT = 1.25 V
0.5 0.4 0.3 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT
5
FREQUENCY
4
ERROR VOLTAGE (V)
0.2 0.1 0 -0.1 -0.2 -0.3 VDD = 5V VREFOUT = 2.5V VDD = 3V VREFOUT = 1.25V
3
2
1
05856-030
-0.4 -8 -6 -4 -2 0 2 CURRENT (mA) 4 6 8 10
05856-031
0
0.92
0.94
0.96 IDD (mA)
0.98
-0.5 -10
Figure 30. IDD Histogram with Internal Reference, VREFOUT = 2.5 V
Figure 33. Headroom at Rails vs. Source and Sink
Rev. PrA. | Page 14 of 32
05856-061
1
1
05856-060
1
Preliminary Technical Data
6 5 4 3 2 1/4 SCALE 1 VDD = 5V VREFOUT = 2.5V TA = 25C FULL SCALE
AD5625R/AD5645R/AD5665R, AD5625/AD5665
3/4 SCALE
MIDSCALE
VDD = VREF = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND
VOUT (V)
VOUT = 909mV/DIV
0 -1 -30 ZERO SCALE
05856-046
1
05856-048
-20
-10
0 10 CURRENT (mA)
20
30
TIME BASE = 4s/DIV
Figure 34. AD56x5R with 2.5V Reference, Source and Sink Capability
4 VDD = 3V VREFOUT = 1.25V TA = 25C FULL SCALE 3/4 SCALE MIDSCALE 1 1/4 SCALE
Figure 37. Full-Scale Settling Time, 5 V
VDD = VREF = 5V TA = 25C
3
VOUT (V)
2
VDD 1
0
ZERO SCALE
2 VOUT
05856-047
MAX(C2) 420.0mV
-1 -30
-20
-10
0 10 CURRENT (mA)
20
30
CH1 2.0V
CH2 500mV
M100s 125MS/s A CH1 1.28V
8.0ns/pt
Figure 35. AD56x5R with 1.25V Reference, Source and Sink Capability
0.50 0.45 0.40 0.35
1
Figure 38. Power-On Reset to 0 V
SYNC
VDD = VREFIN = 5V
VDD = VREFIN = 3V
3
SLCK
IDD (mA)
0.30 0.25 0.20 0.15 0.10 0.05
05856-063
VOUT 2
VDD = 5V
05856-050
TA = 25C 0 -40 -20
0
20 40 60 TEMPERATURE (C)
80
100
CH1 5.0V CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
Figure 36. Supply Current vs. Temperature
Figure 39. Exiting Power-Down to Midscale
Rev. PrA. | Page 15 of 32
05856-049
AD5625R/AD5645R/AD5665R, AD5625/AD5665
2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF)
Preliminary Technical Data
VDD = VREF = 5V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
1
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
05856-058
Y AXIS = 2V/DIV X AXIS = 4s/DIV
Figure 40. Digital-to-Analog Glitch Impulse (Negative)
2.498 2.497 2.496 2.495 2.494 2.493 2.492 2.491 VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
VDD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
10V/DIV
1
05856-059
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
5s/DIV
Figure 41. Analog Crosstalk, External Reference
2.496 2.494 2.492 2.490 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 2.468 2.466 2.464 2.462 2.460 2.458 2.456
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
VDD = 3V VREFOUT = 1.25V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
5V/DIV
1
05856-062
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
4s/DIV
Figure 42. Analog Crosstalk, Internal Reference
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference
Rev. PrA. | Page 16 of 32
05856-053
VDD = 5V VREFOUT = 2.5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 4.462nV
05856-052
05856-051
Preliminary Technical Data
800 700 TA = 25C MIDSCALE LOADED
AD5625R/AD5645R/AD5665R, AD5625/AD5665
16 VREF = VDD TA = 25C 14
OUTPUT NOISE (nV/Hz)
600 500 400 300 200 100 0 100 VDD = 3V VREFOUT = 1.25V
05856-054
VDD = 3V 12
TIME (s)
10
VDD = 5V VREFOUT = 2.5V
8
VDD = 5V
6
1k
10k FREQUENCY (Hz)
100k
1M
0
1
2
3
4 5 6 7 CAPACITANCE (nF)
8
9
10
Figure 46. Noise Spectral Density, Internal Reference
-20 -30 -40 -50 VDD = 5V TA = 25C DAC LOADED WITH FULL SCALE VREF = 2V 0.3V p-p 5 0 -5 -10
Figure 48. Settling Time vs. Capacitive Load
VDD = 5V TA = 25C
(dB)
-60 -70 -80 -90
05856-055
(dB)
-15 -20 -25 -30 -35
2k
4k 6k FREQUENCY (Hz)
8k
10k
100k 1M FREQUENCY (Hz)
10M
Figure 47. Total Harmonic Distortion
Figure 49. Multiplying Bandwidth
Rev. PrA. | Page 17 of 32
05856-057
-100
-40 10k
05856-056
4
AD5625R/AD5645R/AD5665R, AD5625/AD5665 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Zero-Code Error Zero-code error is a measurement of the output error when zero scale (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5665R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as % of FSR. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5665R with code 512 loaded in the DAC register. It can be negative or
positive.
Preliminary Technical Data
Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the rising edge of the STOP condition. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. A plot of noise spectral density can be seen in Figure . DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in V. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in V/mA. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.
DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by 10%.
Rev. PrA. | Page 18 of 32
Preliminary Technical Data
Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB.
Rev. PrA. | Page 19 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665 THEORY OF OPERATION
D/A SECTION
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 50 shows a block diagram of the DAC architecture.
V DD REF (+) DAC REGISTER RESISTOR STRING REF (-) GND OUTPUT AMPLIFIER GAIN = +2 V OUT
Preliminary Technical Data
R
R
R
TO OUTPUT AMPLIFIER
R
Figure 50. DAC Architecture
R
Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by
VOUT = VREFIN
D x N 2
Figure 51. Resistor String
INTERNAL REFERENCE
The AD5625R/AD5645R/AD5665R feature an on-chip reference. Versions without the -R suffix require an external reference. The on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. Versions packaged in 10-lead LFCSP package have a 1.25 V reference, giving a full scale output of 2.5 V. These parts can be operated with a Vdd supply of 2.7V to 5.5V. Versions packaged in 14-lead TSSOP package have a 2.5 V reference, giving a fullscale output of 5 V. Parts are functional with a Vdd supply of 2.7V to 5.5V but for Vdd supply of less than 5V, the output will be clamped to Vdd. See the Ordering Information on the back page for a full list of models. The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor is placed between reference output and GND for reference stability.
The ideal output voltage when using the internal reference is given by D VOUT = 2 x V REFOUT x N 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 4095 for AD5625R/AD5625 (12 bit). 0 to 16,383 for AD5645R (14 bit). 0 to 65,535 for AD5665R/AD5665 (16 bit). N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 51. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
EXTERNAL REFERENCE
The VREFIN pin on the AD56x5R allows the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All devices can be operated from a single 2.7 V to 5.5 V supply.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure and Figure. The slew rate is 1.8 V/s with a 1/4 to 3/4 full-scale settling time of 7 s.
SERIAL INTERFACE
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 have 2wire I2C-compatible serial interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The AD5625R/AD5645R/AD5665R, AD5625/AD5665 can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence.
Rev. PrA. | Page 20 of 32
Preliminary Technical Data
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 support standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) data transfer modes. High-speed operation is only available on selected models. See the Ordering Information on the back page for a full list of models. Support is not provided for 10-bit addressing and general call addressing. The AD5625R/AD5645R/AD5665R, AD5625/AD5665 each have a 7-bit slave address. 10-pin versions of the part have a slave address whose five MSBs are 00011, and the two LSBs are set by the state of the ADDR address pin, which determines the state of the A0 and A1 address bits. 14-pin versions of the part have a slave address whose three MSBs are 001, and the four LSBs are set by the ADDR1 and ADDR2 address pins, which determine the state of the A0 and A1, A2 and A3 address bits respectively. The ADDR pin is three-state, and can be set as shown in Table 8 to give three different addresses.
Table 8. ADDR Pin Settings (10-pin package)
ADDR PIN CONNECTION VDD No Connection GND A1 0 1 1 A0 0 0 1
AD5625R/AD5645R/AD5665R, AD5625/AD5665
The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition.
The ADDR1 and ADDR2 pins are also three-state, and can be set as shown in Table 9 to give a total of 9 different addresses.
Table 9. ADDR1, ADDR2 Pin Setting (14-pin Package)
ADDR2 VDD VDD VDD NC NC NC GND GND GND ADDR1 VDD NC GND VDD NC GND VDD NC GND A3 0 0 0 1 1 1 1 1 1 A2 0 0 0 0 0 0 1 1 1 A1 0 1 1 0 1 1 0 1 1 A0 0 0 1 0 0 1 0 0 1
Rev. PrA. | Page 21 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1 SCL 9 1
Preliminary Technical Data
9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD56x5
DB23 D B22 DB2 1 D B20 DB19 DB 18 D B17 DB1 6 ACK. BY AD56x5 FRAME 2 COMMAND BYTE 9 1 9
FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED)
SDA (CONTINUED)
DB15 DB14 DB 13 D B12 DB 11 D B10
DB 9
D B8 ACK. BY AD56x5
D B7
DB6
DB5
D B4
D B3
D B2
DB 1
DB0 ACK. BY STOP BY AD56x5 MASTER
FRAME 3 MOST SIGNIFICANT DATA BYTE
FRAME 4 LEAST SIGNIFICANT DATA BYTE
Figure 52. I2C Write Operation (10-Pin Package)
1 SCL 9 1 9
SDA START BY MASTER
0
0
1
A3
A2
A1
A0
R/W ACK. BY AD56x5
DB23 DB 22 DB 21 DB2 0 DB19 DB1 8 DB1 7 D B16 ACK. BY AD56x5 FRAME 2 COMMAND BYTE 9 1 9
FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED)
SDA (CONTINUED)
DB15 DB 14 DB1 3 DB1 2 DB 11 D B10
D B9
DB 8 ACK. BY AD56x5
DB7
DB6
DB5
DB4
D B3
DB2
DB 1
DB0 ACK. BY STOP BY AD56x5 MASTER
FRAME 3 MOST SIGNIFICANT DATA BYTE
FRAME 4 LEAST SIGNIFICANT DATA BYTE
Figure 53. I2C Write Operation (14-Pin Package)
WRITE OPERATION
When writing to the AD5625R/AD5645R/AD5665R, AD5625/AD5665, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5665 requires two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must therefore written to the DAC, the command byte followed by the most significant data byte and the least significant data byte, as shown in Figures 52 and 53. All these data bytes are acknowledged by the AD5625R/AD5645R/AD5665R, AD5625/AD5665. A stop condition follows.
READ OPERATION
When reading data back from the AD5625R/AD5645R/AD5665R, AD5625/AD5665, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in Figures 54 and 55. A stop condition follows. Note that the only data that can be read back from the AD56x5 is the contents of the input shift register (see section on Control Register).
Rev. PrA. | Page 22 of 32
Preliminary Technical Data
1 SCL 9
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD56x5
DB23 DB 22 D B21 DB 20 DB1 9 DB 18 D B17 DB 16 ACK. BY MASTER FRAME 2 COMMAND BYTE 9 1 9
FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED)
SDA (CONTINUED)
DB15 DB14 D B13 DB12 D B11 DB1 0
DB 9
D B8 ACK. BY MASTER
DB7
DB6
DB 5
D B4
D B3
DB 2
D B1
DB 0 NO ACK. STOP BY MASTER
FRAME 3 MOST SIGNIFICANT DATA BYTE
FRAME 4 LEAST SIGNIFICANT DATA BYTE
Figure 54. I2C Read Operation(10-Pin Package)
1 SCL 9 1 9
SDA START BY MASTER
0
0
1
A3
A2
A1
A0
R/W ACK. BY AD56x5
DB23 DB 22 DB2 1 DB20 DB 19 DB1 8 DB1 7 DB 16 ACK. BY MASTER FRAME 2 COMMAND BYTE 9 1 9
FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED)
SDA (CONTINUED)
DB15 D B14 DB 13 DB 12 DB1 1 DB1 0 D B9
DB8 ACK. BY MASTER
DB 7
DB 6
DB5
D B4
DB3
DB 2
DB1
D B0 NO ACK. STOP BY MASTER
FRAME 3 MOST SIGNIFICANT DATA BYTE
FRAME 4 LEAST SIGNIFICANT DATA BYTE
Figure 55. I2C Read Operation(14-Pin Package)
HIGH SPEED MODE
Some models offer high-speed serial communication with a clock frequency of 3.4 MHz. See the Ordering Information on the back page for a full list of models. High speed mode communication commences after the master addresses all devices connected to the bus with the Master Code 00001XXX to indicate that a high speed mode transfer is to begin. No device connected to the bus is permitted to
FAST MODE 1 SCL 9 1
acknowledge the high speed master code, therefore, the code is followed by a no acknowledge. The master must then issue a repeated start followed by the device address. The selected device then acknowledges its address. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to standard/fast mode. The part will also exit high speed mode if CLR is activated while part is in high speed mode..
HIGH-SPEED MODE 9
SDA START BY MASTER
0
0
0
0
1
X
X
X NACK SR
0
0
0
1
1
A1
A0
R/W ACK. BY AD56x5
HS-MODE MASTER CODE
SERIAL BUS ADDRESS BYTE*
*NOTE: ADDRESS SHOWN IS FOR 10-PIN DEVICE. ADDRESS FOR 14-PIN DEVICE IS 001(A3)(A2)(A1)(A0)
Figure 56. Placing the AD56x5 in High-Speed Mode
Rev. PrA. | Page 23 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
MULTIPLE BYTE WRITE
Once an AD56x5 has been addressed, one or more three-byte blocks of command and data can be sent to the device, until a stop condition is received. The device must then be readdressed. For this type of operation, the "S" bit in the command byte is set to zero. For some types of application such as waveform generation, it may be required to update a DAC or DACs as fast as possible without changing the command byte. In this case the "S" bit in the initial command byte is set to 1. This sets the command
parameters for all subsequent data. Thereafter, multiple twobyte blocks of data high byte and data low byte can be sent, without sending a further command byte, until a stop condition is received. The "S" bit is only active in the first command byte following the device slave address. Therefore, even if the "S" bit is 0 and three-byte blocks of command and data are being sent, it is not possible to alter the multi-byte mode by changing the "S" bit to 1 "on-the-fly" during any subsequent command byte.
BLOCK n S=0 COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP BYTE DATA BYTE DATA BYTE
BLOCK 1 BLOCK 2 S=0 S=0 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE
Figure 57. Multiple Block Write With Command Byte in Each Block (S=0)
BLOCK 1 BLOCK 2 S=1 S=1 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE
BLOCK n S=1 MOST SIGNIFICANT LEAST SIGNIFICANT STOP DATA BYTE DATA BYTE
Figure 58. Multiple Block Write With Initial Command Byte Only (S=1)
BROADCAST MODE
In addition to the unique slave address for each device, which is set by the address pin(s), The AD56x5 has a broadcast address to which any AD56x5 will respond, irrespective of the state of the address pin(s). This address is 0001000(Write). Where several AD56x5 devices are connected to a bus, they can all be sent the same data using the broadcast address. The broadcast address only works for write operations. It is not possible to read back data from several devices at the same time, due to bus contention. - a three-bit address that tells the device to which DAC or DACs the command applies. - 16 bits of data, which, depending on the command may be written to a DAC or used to define the parameters of a command operation. Bit 23 of the input shift register is reserved, and should always be set to 0 when writing to the device. The command and address are contained in the command byte, the 8 MSBs of the input register. The middle 8 bits are the high byte of the DAC data, while the 8 least significant bits are the low byte of the DAC data or command data. DAC data is left justified, so the two LSBs are unused for the 14 bit AD5645R, and the four LSBs are unused for the 12-bit AD5625R (but they are still used for command data in these devices. The AD56x5 has seven different commands that can be written to it.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide to store the 3 data bytes written to the device of the serial interface. Data written to the device is split into four sections: - One bit to select multiple byte operation. - a three bit command that tells the device what operation to perform.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R
RESERVED
DB9 D9
DB8 D8
DB7 D7
DB6 D6
DB5 D5
DB4 D4
DB3 D3
DB2 D2
DB1 D1
DB0 D0
S
BYTE SELECTION
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
COMMAND
DAC ADDRESS
DAC DATA
DAC OR COMMAND DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 59. AD5665R/AD5665 Input Shift Register (16-Bit DAC)
Rev. PrA. | Page 24 of 32
Preliminary Technical Data
AD5625R/AD5645R/AD5665R, AD5625/AD5665
DB9 D7 DB8 D6 DB7 D5 DB6 D4 DB5 D3 DB4 D2 DB3 D1 DB2 D0 DB1 X DB0 X
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R
RESERVED
S
BYTE SELECTION
C2
C1
C0
A2
A1
A0
D13
D12
D11
D10
D9
D8
COMMAND
DAC ADDRESS
DAC DATA
DAC OR COMMAND DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 60. AD5645R Input Shift Register (14-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R
RESERVED
DB9 D5
DB8 D4
DB7 D3
DB6 D2
DB5 D1
DB4 D0
DB3 X
DB2 X
DB1 X
DB0 X
S
BYTE SELECTION
C2
C1
C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
COMMAND
DAC ADDRESS
DAC DATA
DAC OR COMMAND DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 61. AD5625R/AD5625 Input Shift Register (12-Bit DAC)
WRITE COMMANDS AND LDAC
Table 10. Command Definition
C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Command Write to input register n Update DAC register n Write to input register n, update all (software LDAC) Write to and update DAC channel n Power up/power down Reset LDAC register setup Internal reference setup (on/off )
Table 10 is the truth table for the command bits. The DAC or DACs on which a command is performed is/are defined by n, which is the DAC address shown in table 11. Some commands required additional data which is defined in the low data byte.
Table 11. DAC Address Command
A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B DAC C DAC D All DACs
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 DACs have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings.
The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. For example, the user could write to three of the input registers individually and then write to the remaining input register and, updating all DAC registers, the outputs will update simultaneously. The AD56x5 has a powerful set of commands for writing to and updating the DACs. The 14-pin version also has a hardware load DAC (LDAC) pin. It is important to understand how these commands and the LDAC pin operate and interact with each other, in order to ensure that the desired result is obtained. The first four commands are used for writing to and updating the DACs. Command 000 writes to input register n, without updating the DAC registers, where n is the input register defined by the A2 -A0 bits in the command byte. Depending on the value of A2 -A0, this can be any one of the input registers or all four input registers, as defined b y the DAC address. Command 001 does not write to the input registers, but (depending on the value of A2 -- A0) updates a DAC register or all four DAC registers. Command 010 writes to input register n, and updates all DAC registers. Command 011 writes to input register n and updates DAC register n. Since n can be all DACs (A2 -- A0 = 111) commands 010 and 011 are equivalent if A2 -- A0 = 111. -
LDAC SETUP
In addition to the write commands, the LDAC setup command (110) can also determine which DACs are updated at the end of a write operation (this command does not update the DACs when it is implemented). It also affects the operation of the
Rev. PrA. | Page 25 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
LDAC pin on the 14-pin device (see below). When this command is sent to the device, data bits DB3 to DB0 determine which of DAC registers D through A are updated at the end of write. If a bit is set to 1, the corresponding DAC is updated. Note that, during the LDAC setup command, the DAC address bits A2 - A0 are ignored. It is only DB3 to DB0 that determine which DAC will be updated.
Preliminary Technical Data
As far as DAC updating is concerned, the write command and the LDAC setup command are combined (OR'd together). For example, if the LDAC setup command is set to update DACs B and D, and command 011 is sent to write to and update DAC A, then DAC A will be written to, but DACs A, B and D will be updated.
R 0
S X
C2 1
C1 1 COMMAND
C0 0
A2 A2
A1 A1
A0 A0
DB15 DB14 DB13 DB12 DB11 X X X X X
DB10 X
DB9 X
DB8 X
DB7 X
DB6 X
DB5 X
DB4 X
DB3
DB2
DB1
DB0
DACD DACC DACB DACA DAC SELECT (0 = LDAC PIN ENABLED)
DON'T RES CARE
DAC ADDRESS (DON'T CARE)
DON'T CARE
DON'T CARE
Figure 62. LDAC Setup Command
LDAC PIN
In the case of the 14-pin device, updating of the DAC registers may also be controlled by the LDAC pin. This can operate either synchronously or asynchronously. Whenever LDAC is brought low, the DAC registers are updated with the contents of the input registers. If LDAC is held low, update takes place synchronously at the end of every write operation. Which DAC registers are updated when LDAC is brought low is determined by the LDAC setup command. It is the inverse of those registers that are set to update at the end of write. If one of bits DB3 to DB0 is a 0, then the corresponding DAC is updated when LDAC is taken low. If it is a 1, the DAC is updated at the end of a write operation. This allows some DACs to be updated automatically at the end of write, and some to be updated asynchronously using the LDAC pin. If LDAC is permanently held low for synchronous update, then all DACs will be updated irrespective of the DAC address in the write command or the bit settings in the LDAC setup command. This is because those DACs whose bits are 0 in LDAC setup will be updated due to the LDAC pin being low, and those DACs whose bits are 1 will be updated due to the LDAC setup command. If DAC update is to be controlled solely by the write and LDAC setup commands, the LDAC pin must be tied high (or use the 10-pin device which does not have this pin). If DAC update is to be controlled solely by the LDAC pin, then use only command 000 and set DB3 to DB0 to 0 in the LDAC setup command. These parts each contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD56X5, the DAC register updates only if the input register has changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk.
POWER-DOWN MODES
R 0 S X C2 1 C1 0 COMMAND C0 0 A2 A2 A1 A1 A0 A0 DB15 DB14 DB13 DB12 DB11 X X X X X DB10 X DB9 X DB8 X DB7 X DB6 X DB5 PD1 DB4 PD0 DB3 DB2 DB1 DB0
DACD DACC DACB DACA DAC SELECT (1 = DAC SELECTED)
DON'T RES CARE
DAC ADDRESS (DON'T CARE)
DON'T CARE
POWER DON'T CARE DOWN MODE
Figure 63. Power Up/down Command
Command 100 is the power up/down function. The parameters of the power up/down function are programmed by bits DB5 and DB4. This defines the output state of the DAC amplifier, as shown in Table 12. Bits DB3 to DB0 determine to which DAC or DACs the power up/down command is applied. Setting the one of these bits to 1 applies the power up/down state defined by DB5 and DB4 to the corresponding DAC. If a bit is 0, the state of the DAC is unchanged.
In power-down mode, the amplifier is disconnected from the output pin, and the output pin is either open-circuit or connected ground via a 10k or 100k resistor, depending on the setting of DB5 and DB4.
Table 12. Modes of Operation for the AD5625R/AD5645R/AD5665R, AD5625/AD5665
DB5 0 DB4 0 Operating Mode Normal operation
Rev. PrA. | Page 26 of 32
Preliminary Technical Data
0 1 1 1 0 1 Power-down modes 1 k pulldown to GND 100 k pulldown to GND Three-state, high impedance
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Any events on LDAC or CLR during power-on reset are ignored. There is also a software reset function. Command 101 is the software reset command. The software reset command contains two reset modes that are software programmable by setting bit DB0 in the input shift register.
VOUT
RESISTOR STRING DAC
AMPLIFIER
Figure 64. Output Stage During Power-Down
05856-038
POWER-DOWN CIRCUITRY
Table 13 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Figure 64 shows the contents of the input shift register during the software reset mode of operation.
Table 13. Software Reset Modes for the AD5625R/AD5645R/AD5665R, AD5625/AD5665
DB0 0 1 (Power-On Reset) Registers reset to zero DAC register Input shift register DAC register Input shift register LDAC register Power-down register Internal reference setup register
RESISTOR NETWORK
The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 s for VDD = 5 V and for VDD = 3 V. Figure 63 shows the format of the power up/down command. Note that, during the power up/down command, the DAC address bits A2 - A0 are ignored.
POWER-ON-RESET AND SOFTWARE RESET
The AD56x5 contains a power-on reset circuit that controls the output voltage during power-up. The 10-pin version of the device powers up to 0V. The 14-pin version has a Power On Reset (POR) pin that allows the output voltage to be selected. By connecting the POR pin low, the AD56x5 output powers up to 0 V; by connecting the POR pin high, the AD56x5 output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
CLEAR PIN (CLR)
The 14-pin version of the AD56x5 has an asynchronous clear input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode to fast mode.
Figure 65. Reset Command
INTERNAL REFERENCE SETUP (-R VERSIONS)
The on-chip reference is off at power-up by default. It can be turned on by sending the reference setup command (111) and setting DB0 in the input shift register. Table 14 shows how the state of the bit corresponds to the mode of operation.
Table 14. Reference Setup Command
(DB0) 0 1 Action Internal reference off (default) Internal reference on
Rev. PrA. | Page 27 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
Figure 66. Reference Setup Command
Rev. PrA. | Page 28 of 32
Preliminary Technical Data APPLICATIONS
USING A REFERENCE AS A POWER SUPPLY FOR THE AD5625R/AD5645R/AD5665R, AD5625/AD5665
Because the supply current required by the AD5625R/AD5645R/AD5665R, AD5625/AD5665is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5625R/AD5645R/AD5665R, AD5625/AD5665. If the low dropout REF195 is used, it must supply 450 A of current to the AD5625R/AD5645R/AD5665R, AD5625/AD5665 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 k load on the DAC output) is 450 A + (5 V/5 k) = 1.45 mA The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 2.9 ppm (14.5 V) error for the 1.45 mA current drawn from it. This corresponds to a 0.191 LSB error.
15V REF195 5V V DD 2-WIRE SCL SERIAL INTERFACE SDA AD5625(R)/ AD5645R/ AD5665(R) GND V OUT = 0V TO 5V
AD5625R/AD5645R/AD5665R, AD5625/AD5665
This is an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output, and 0xFFFF corresponding to a +5 V output.
R2 = 10k R1 = 10k V DD 0.1F GND SCL SDA 2-WIRE SERIAL INTERFACE AD5625(R)/ AD5645R/ AD5665(R) AD820/ V OUT OP295 -5V +5V 5V
+5V 10F
Figure 68. Bipolar Operation with the AD5625R/AD5645R/AD5665R, AD5625/AD5665
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5625R/AD5645R/AD5665R, AD5625/AD5665 should have separate analog and digital sections, each having its own area of the board. If the AD5625R/AD5645R/AD5665R, AD5625/AD5665 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5625R/AD5645R/AD5665R, AD5625/AD5665. The power supply to the AD5625R/AD5645R/AD5665R, AD5625/AD5665 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be located as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitor is the tantalum bead type. It is important that the 0.1 F capacitor have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
Figure 67. REF195 as Power Supply to the AD5625R/AD5645R/AD5665R, AD5625/AD5665
BIPOLAR OPERATION USING THE AD5625R/AD5645R/AD5665R, AD5625/AD5665
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 67. The circuit gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
D R1 + R2 R2 VO = VDD x x - VDD x R1 65,536 R1
where D represents the input code in decimal (0 to 65535). With VDD = 5 V, R1 = R2 = 10 k,
10 x D VO = -5 V 65,536
Rev. PrA. | Page 29 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
Rev. PrA. | Page 30 of 32
Preliminary Technical Data OUTLINE DIMENSIONS
INDEX AREA
AD5625R/AD5645R/AD5665R, AD5625/AD5665
3.00 BSC SQ
10
PIN 1 INDICATOR
1
1.50 BCS SQ
TOP VIEW
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
2.48 2.38 2.23
5
6
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 TYP
SIDE VIEW
0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF
1.74 1.64 1.49
0.30 0.23 0.18
Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19
0.20 0.09
SEATING COPLANARITY PLANE 0.10
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 70. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
Rev. PrA. | Page 31 of 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665
ORDERING GUIDE
Model AD5625BCPZ-250RL71 AD5625BCPZ-REEL71 AD5625BRUZ1 AD5625BRUZ-REEL71 AD5625RBCPZ-250RL71 AD5625RBCPZ-REEL71 AD5625RBRUZ-11 AD5625RBRUZ-1REEL71 AD5625RBRUZ-21 AD5625RBRUZ-2REEL71 AD5645RBCPZ-250RL71 AD5645RBCPZ-REEL71 AD5645RBRUZ1 AD5645RBRUZ-REEL71 AD5665BCPZ-250RL71 AD5665BCPZ-REEL71 AD5665BRUZ1 AD5665BRUZ-REEL71 AD5665RBCPZ-250RL71 AD5665RBCPZ-REEL71 AD5665RBRUZ-11 AD5665RBRUZ-1REEL71 AD5665-RBRUZ-21 AD5665RBRUZ-2REEL71
1
Preliminary Technical Data
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Accuracy 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL
On-Chip Reference None None None None 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V None None None None 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V
Max I2C Speed 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 3.4 MHz 3.4 MHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 3.4 MHz 3.4 MHz
Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP
Package Option CP-10 -9 CP-10-9 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 RU-14 RU-14
Branding D8V D8V None None D8S D8S None None None None D89 D89 None None D6U D6U None None DA2 DA2 None None None None
Z = Pb-free part.
Rev. PrA. | Page 32 of 32
PR06341-0-8/06(PrA)

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